This invention relates generally to integrated circuit processes and fabrication, and more particularly, to an integrated circuit and method of differentially depositing copper on selected integrated circuit surfaces.
The demand for progressively smaller, less expensive, and more powerful electronic products, in turn, fuels the need for smaller geometry integrated circuits (ICs), and large substrates. It also creates a demand for a denser packaging of circuits onto IC substrates. The desire for smaller geometry IC circuits requires that the interconnections between components and dielectric layers be as small as possible. Therefore, research continues into reducing the width of via interconnects and connecting lines. The conductivity of the interconnects is reduced as the surface area of the interconnect is reduced, and the resulting increase in interconnect resistivity has become an obstacle in IC design. Conductors having high resistivity create conduction paths with high impedance and large propagation delays. These problems result in unreliable signal timing, unreliable voltage levels, and lengthy signal delays between components in the IC. Propagation discontinuities also result from intersecting conduction surfaces that are poorly connected, or from the joining of conductors having highly different impedance characteristics.
There is a need for interconnects and vias to have both low resistivity, and the ability to withstand volatile process environments. Aluminum and tungsten metals are often used in the production of integrated circuits for making interconnections or vias between electrically active areas. These metals are popular because they are easy to use in a production environment, unlike copper which requires special handling.
Copper (Cu) is a natural choice to replace aluminum in the effort to reduce the size of lines and vias in an electrical circuit. The conductivity of copper is approximately twice that of aluminum and over three times that of tungsten. As a result, the same current can be carried through a copper line having half the width of an aluminum line.
The electromigration characteristics of copper are also much superior to those of aluminum. Aluminum is approximately ten times more susceptible than copper to degradation and breakage due to electromigration. As a result, a copper line, even one having a much smaller cross-section than an aluminum line, is better able to maintain electrical integrity.
There have been problems associated with the use of copper, however, in IC processing. Copper pollutes many of the materials used in IC processes and, therefore, care must be taken to keep copper from migrating. The migration of copper into silicon semiconductor regions is especially harmful. The conduction characteristics of the semiconductor regions are a consideration in the design of a transistors. Typically, the fabrication process is carefully controlled to produce semiconductor regions in accordance with the design. Elements of copper migrating into these semiconductor regions can dramatically alter the conduction characteristics of associated transistors.
Various means have been suggested to deal with the problem of copper diffusion into integrated circuit material. Several materials, especially metallic ones, have been suggested for use as barriers, at least partially encapsulating copper structures, to prevent copper diffusion into susceptible circuits. Tungsten, molybdenum, and titanium nitride (TiN) have also been suggested for use as copper diffusion barriers. By using a metallic barrier material copper can electrically communicate with semiconductor regions, and yet be physically isolated. However, the adhesion of copper to these diffusion barrier materials has been an IC process problem, and the electrical conductivity of such materials is an issue in building IC interconnects.
The deposition of copper on IC surfaces, as mentioned above, is a process problem. It is inconvenient to cover an IC surface with a layer of copper, and then etch portions of the copper layer to form interconnect structures as is done with other metals. Copper is removed at high temperatures, which potentially harms associated silicon, oxide, semiconductor, and metal structures. Since copper is typically deposited at high temperatures, it is difficult to use photoresist as a mask to cover areas of an IC surface where an application of CVD copper is not desired. Photoresist becomes degraded at high temperatures. Therefore, copper interconnect features are often formed with a currently developing damascene method.
The damascene method for forming a via between a substrate surface and an overlying dielectric surface is described below. The underlying substrate surface is first completely covered with a dielectric, such as oxide. A patterned photoresist profile is then formed over the oxide. The resist profile has an opening, or hole, in the photoresist corresponding to the area in the oxide where the via is to be formed. Other areas of the oxide to be left in place are covered with photoresist. The photoresist covered dielectric is then etched to remove oxide underlying the hole in the photoresist. The photoresist is then stripped away. CVD copper is then used to fill the via. A layer consisting of oxide with a copper via through it now overlies the substrate surface. The excess copper remaining is removed with a chemical mechanical polish (CMP) process, as is well known in the art.
Besides adhesion and etching difficulties, it is also a problem to deposit copper onto a substrate, or in a via, using the conventional processes for the deposition of aluminum when the geometries of the selected IC features are small. That is, new deposition processes have been developed for use with copper, instead of aluminum, in the lines and interconnects of an IC interlevel dielectric. It is impractical to sputter metal, either aluminum or copper, to fill small diameter vias, since the gap filling capability is poor. To deposit copper, first, a physical vapor deposition (PVD), and then, a chemical vapor deposition (CVD) technique have been developed by the industry.
With the PVD technique, an IC surface is exposed to a copper vapor and copper condenses on the surfaces. The technique is not selective with regard to surfaces. When copper is to be deposited on a metallic surface, adjoining non-conductive surfaces must either be masked or etched clean in a subsequent process step. As mentioned earlier, photoresist masks and other adjoining IC structures are typically damaged at the high temperatures at which copper is vaporized. The CVD technique is an improvement over PVD because it is more selective as to which surfaces copper is deposited on. The CVD technique is selective because it relies on a chemical reaction between the metallic surface and the copper vapor to cause the deposition of copper on the metallic surface.
In a typical CVD process, copper is combined with a ligand, or organic compound, to make the copper volatile. That is, copper becomes an element in a compound that is vaporized into a gas. Selected surfaces of an integrated circuit, such as diffusion barrier material, are exposed to the copper gas, or precursor, in an elevated temperature environment. When the copper gas compound decomposes, copper is left behind on the selected surface. Several copper gas compounds are available for use with the CVD process. It is generally accepted that the configuration of the copper gas compound, at least partially, affects the ability the copper residue to adhere itself to the selected surface.
Norman et al., U.S. Pat. No. 5,085,731, discloses precursors to deposit copper on conductive surfaces. These precursors react chemically to selectively deposit copper on metallic conductive surfaces, but not non-metallic surfaces. However, the application of CVD copper typically becomes less selective the longer the process continues. After a period of time, copper eventually begins to accumulate on the non-conductive surface. Once a layer of copper is established on the non-conductive surface, the growth rates of deposited copper on conductive and non-conductive surfaces are substantially the same.
It would be advantageous if copper could be deposited on IC surfaces without the necessity of masking non-conductive surfaces, or performing a substantial etching process to remove copper from non-conductive surfaces.
It would be advantageous if copper interconnects, studs, and lines could be formed without the necessity of using a damascene process to protect adjoining non-conductive surfaces.
It would be advantageous to employ a method of selectively depositing copper on conductive and non-conductive IC surfaces. Further, it would be advantageous to selectively deposit copper to adjoining conductive and non-conductive surfaces.
It would be advantageous if a method were employed for preparing both conductive and non-conductive surfaces, in advance of an application of CVD copper, to improve the selectivity of the copper deposited on the surfaces.
Accordingly, a method of differentially depositing copper on selected IC surfaces is provided. The selected surfaces include conductive and non-conductive surfaces applied to selected regions of the IC. The method comprising the steps of: exposing each selected surface to a source of ions; etching each selected surface to remove contaminants and undesired IC materials that have collected on the non-conductive surface; and applying CVD Cu to each selected surface, forming a relatively thick layer of Cu overlying conductive surfaces, and a relatively thin layer of Cu overlying the non-conductive surfaces, whereby the exposure of the selected surfaces promotes variations in the rates at which Cu is deposited.
Preferably, the three process steps, mentioned above, are repeated a plurality of times to differentially deposit copper on each selected surface a plurality of times. The undesired IC material removed from the non-conductive surface is copper, whereby the layer of copper overlying the conductive surface is made progressively thicker while maintaining a copper-free non-conductive surface. Cu is deposited on each selected surface until less than approximately a monolayer of Cu is accumulated on the non-conductive surface. Then, each selected surface is etched until the Cu accumulated on the non-conductive surface is removed.
The source ions, to which each selected surface is exposed, are generated from an inert gas, whereby chemical reactions between the ions and the selected surfaces are minimized. The inert gas is selected from the group consisting of Ar, He, Ne, Kr, H.sub.2, N.sub.2, and Xe. The source ions have an energy level of generally less than 150 eV to control the smoothness of the non-conductive surfaces, and to minimize the etching of non-conductive surface material. The selected surfaces are exposed to a source of ions in a low pressure environment of less than approximately 10 mT, whereby the ion bombardment is anisotropic.
Also provided is an adherent copper conductor interface on an integrated circuit (IC) formed from the differential deposition of Cu on the IC. The Cu conductor interface comprises a conductive surface of IC material, and a non-conductive surface of IC material. The Cu interface also comprises a layer of Cu overlying said conductive surface. The Cu layer is formed through repeated deposition cycles with each deposition cycle including an exposure of both conductive and non-conductive surfaces to a low energy ion source of an inert gas to etch the IC surfaces, followed by an application of CVD Cu to deposit a relatively thin layer of Cu on the non-conductive surface and a relatively thick layer of Cu on the conductive surface. In this manner, Cu is selectively deposited on conductive and non-conductive IC surfaces to form an interconnect between the conductive surface and other regions of the IC.